1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device including a delay circuit.
2. Description of the Related Art
Delay circuits are included in a semiconductor device using an inverter chain in which inverters coupled in series or using a resistor-capacitor (RC) delay circuit. The inverter chain delays a signal by using gate delays (i.e., transmission delays) of transistors forming the inverters. The characteristics of the transistors in the semiconductor device are changed by Process/Voltage/Temperature (PVT) variation. Furthermore, the transistors arranged in the semiconductor device may show undesired characteristics due to a difference between gate patterning processes of the respective transistors or a difference in dose between implantation processes for determining a threshold voltage. In this case, the performance of semiconductor products may be degraded.
Since the RC delay circuit exhibits a smaller skew variation for the PVT variation than the inverter chain implemented with gate delays, the RC delay circuit is used in various circuits. A long-RC delay circuit having a large delay amount exhibits a small skew variation. On the other hand, a short-RC delay circuit having a small delay amount exhibits a skew variation greater than that of the long-RC delay circuit. Thus, the use of the short-RC delay circuit is limited.
The long-RC delay circuit is also used to determine a refresh operation period in DRAMs. For example, a refresh cycle time tRFC used during a refresh operation may be set through the long-RC delay circuit having a considerably large delay amount. However, considering the efficiency of the circuit area of DRAMs, the short-RC delay circuit and a circuit using a counter may be used to set the refresh cycle time tRFC. Since an active operation period by the refresh operation is changed due to the PVT variation, the retention time of DRAM cells may be changed, which makes it difficult to manage the refresh characteristic.
Thus, there is a demand for a short-RC delay circuit which has a less skew while exhibiting the efficiency of the circuit area of DRAMs.